1. Field of the Invention
The present invention relates to a liquid crystal display apparatus and a manufacturing method for the same, and more particularly to a multi-domain liquid crystal display apparatus, in which a liquid crystal layer is divided into a plurality of domains by control electrodes and a manufacturing method for the same.
2. Description of the Related Art
An active matrix drive type liquid crystal display apparatus using an active device such as a thin film transistor has characteristics such as a small size, a thin type and a low power consumption. Therefore, such a liquid crystal display apparatus has come to practical use in the fields of office automation (OA) equipment and audio and video (AV) equipment. Various driving system are known for the liquid crystal display apparatus. A liquid crystal display apparatus of a vertical electric field, i.e., a twisted nematic (TN) type is mainly used and is disclosed in Japanese Laid Open Patent application (JP-A-Heisei 10-68971). In the TN type, a liquid crystal layer is interposed between two substrates and the liquid crystal layer is driven in response to the voltage applied between the substrates.
In the typical active matrix drive type TN liquid crystal display apparatus, one of the above substrates is composed of a drain wiring line and a gate wiring line extending in orthogonal directions to each other, a the pixel electrode formed in the region surrounded by these wiring lines, and a thin film transistor (TFT) formed in the neighborhood of an intersection of the gate wiring line and the drain wiring line. Also, an orientation film is formed on the TFT and the pixel electrode of the substrate. The orientation film is used to drive liquid crystal molecules to turn to predetermined direction. A color filter, a common electrode, an orientation film are formed by a counter substrate as the other substrate. To form a liquid crystal display apparatus, a liquid crystal layer is interposed between the above substrate and the counter substrate.
A manufacturing method of such a conventional TN-type liquid crystal display apparatus will be described. FIG. 1A to FIG. 5D are diagrams schematically showing the conventional manufacturing method of a substrate of the active matrix drive type TN type liquid crystal display apparatus. FIGS. 1A, 2A, 3A, 4A and 5A are plan views of one pixel, respectively. FIGS. 1B, 2B, 3B, 4B and 5B are cross sectional views of a TFT section along the A-Axe2x80x2 lines of the plan views, respectively. FIGS. 1C, 2C, 3C, 4C and 5C are cross sectional views of a gate terminal section along the B-Bxe2x80x2 lines of the plan views, respectively. FIGS. 1D, 2D, 3D, 4D and 5D are cross sectional views of a drain terminal section along the C-Cxe2x80x2 lines of the respective plan views, respectively.
As shown in FIG. 1A to FIG. 1D, a Cr layer as a gate electrode metal layer is deposited on a transparent insulative substrate (a TFT substrate) 1 by a sputtering method, and a resist pattern is formed using a first photomask. A Cr layer exposed by a lithography process using the resist pattern is etched and a gate bus line 2, a common capacitance line 10 and a gate terminal 2a are formed.
Next, as shown in FIGS. 2A to 2D, the first insulating film 3 composed of silicon nitride (SiNx) film, an amorphous silicon (a-Si) film 4a, an n+-type amorphous silicon film 4b as an ohmic contact film are continuously formed by a CVD (Chemical Vapor Deposition) method. After that, a resist pattern is formed using a second photomask, and the n+-type amorphous silicon film 4b exposed by a lithography process using the resist pattern and the amorphous silicon film 4a are removed by a dry etching using the resist pattern, to form an island 4.
Subsequently, as shown in FIGS. 3A to 3D, a Cr layer as a source/drain metal layer is formed by a sputtering method. After that, a resist pattern is formed using a third photomask and the Cr layer exposed by a lithography process using the resist pattern is removed by a wet etching using the resist pattern. Thus, source/drain electrodes 5b and 5c of a pixel transistor (TFT: thin film transistor), a drain bus line 5 and a drain terminal 5a are formed. After that, using the Cr layer of the source/drain electrodes as an etching mask, the n+-type amorphous silicon film 4b in the channel region is etched to form the pixel transistor.
Next, as shown in FIGS. 4A to 4D, a second insulating film 7 of silicon nitride SiNx is deposited on the transparent insulative TFT substrate 1, and the second insulating film 7 and the first insulating film 3 are exposed using a fourth photomask and is etched. In this way, openings 8a and 8b of the source/drain terminal are formed. After that, as shown in FIG. 5A to FIG. 5D, an ITO film is deposited on the transparent insulative TFT substrate 1. After that, the ITO film exposed using a fifth photomask is removed, and the pixel electrode 9 and gate/drain terminal electrodes are formed to connect with the source electrode 5c. Subsequently, an orientation film is formed on the pixel transistor on this TFT substrate and on the pixel electrode 9 to make liquid crystal to direct to a predetermined direction. After that, a liquid crystal layer is interposed between this TFT substrate and a counter substrate, so that a liquid crystal display apparatus is completed. Other components such as a color filter, a common electrode, and an orientation film are formed on the counter substrate.
In such a conventional TN-type liquid crystal display apparatus, in the display state of xe2x80x9cwhitexe2x80x9d in no voltage application, a liquid crystal molecule has the orientation which is parallel to the TFT substrate. The orientation of the liquid crystal molecule changes from the display state of xe2x80x9cwhitexe2x80x9d to the direction of an electric field in accordance with the application voltage. As a result, the display state changes from the display state of xe2x80x9cwhitexe2x80x9d to the display state of xe2x80x9cblackxe2x80x9d gradually. The TN-type liquid crystal display apparatus has a small view angle because of the peculiar behavior of the liquid crystal molecules in this voltage application. Also, there is a case where an electric field in the lateral direction is generated due to the unevenness of the TFT substrate and the potential difference between the electrodes in the liquid crystal cell. The existence of the electric field in the lateral direction causes a region where the orientations of liquid crystal molecules are different from each other. As a result, discrimination occurs in the boundary of this region.
For the purpose of the improvement of the above mentioned narrow view angle and discrimination in the conventional TN-type liquid crystal display apparatus, it is proposed to use the liquid crystal having negative permittivity anisotropy. The proposal is given in Japanese Laid Open Patent applications (JP-A-Heisei 6-43461, JP-A-Heisei 7-199190, JP-A-Heisei 7-230097 and JP-A-Heisei 10-20323). In a multi-domain liquid crystal display apparatus in these proposals, a liquid crystal cell is formed such that the liquid crystal has homeotropic orientation in a perpendicular direction. Also, an opening is provided for a common electrode or the pixel electrode, and an oblique electric field is generated in each pixel to form a plurality of domains in the pixel.
Especially, in Japanese Patent Application Nos. (Heisei 11-180615 and Heisei 11-359411) which have been filed by the assignee of the present invention, a control electrode is provided to control the orientation state of liquid crystal. However, these applications were not laid opened until two Japanese Patent Applications corresponding to the present application were filed. The pixel electrode in an electrically floating state is connected through a capacity with the control electrode which is connected in turn with the source electrode. This structure is called a floating pixel electrode structure. In accordance with this structure, a pixel transistor of each pixel controls the control electrode and two electrode potentials of the control electrode and the pixel electrode can be controlled easily.
The liquid crystal display apparatus having such a floating pixel electrode structure will be described below. Drain wiring lines and gate wiring lines extend in orthogonal directions to each other on a pixel transistor (TFT) substrate, and one pixel is formed a region surrounded by these wiring lines. Each pixel has a pixel transistor, the pixel electrode and a control electrode. Also, the pixel electrode is in an electrically floating state and forms coupling capacitances together with the control electrode and a common capacitance line through the insulating film, respectively. The pixel transistor substrate and a counter substrate on which counter electrodes are formed are opposed to each other to have a predetermined interval and the liquid crystal having negative permittivity anisotropy is interposed between the substrates.
When a gate bus line is selected, a signal voltage is applied from the drain bus line to the control electrode which is connected with the source terminal through the pixel transistor. At this time, the potential of the pixel electrode in the electrically floating state is set to a potential between the potential of the control electrode and the potential of the common capacitance line in accordance with the ratio of coupling capacitances. Therefore, the potentials are larger or smaller in the order of the control electrode, the pixel electrode and the common capacitance line. Thus, the liquid crystal drive electric field generated between the pixel electrode and the control electrode or the common capacitance line is generated in an oblique direction to spread from the control electrode toward the outside. Therefore, in the one pixel surrounded by the gate lines and the drain lines, it is possible to direct the liquid crystal molecules to different directions on both sides of the control electrode, so that the view angle visual characteristic can be improved.
However, in order to manufacture the multi-domain liquid crystal display apparatus, the process for forming the control electrode must be added at least, compared with the conventional TN-type liquid crystal display apparatus. Especially, in the above mentioned multi-domain liquid crystal display apparatus, it is necessary to form capacitances between the pixel electrode and the control electrode and between the pixel electrode and the common capacitance line. Therefore, the manufacturing method is not yet established and the establishment of the manufacturing method of a high manufacture yield is demanded.
Also, the pixel electrode is in the electrically floating state in the above liquid crystal display apparatus. Therefore, it is easy to undergo influence of the potential of the bus line and influence of the charging of the substrate. The orientations of the liquid crystal molecules are disordered due to these unintentional potential so that display irregularity is easy caused. Therefore, in the liquid crystal display apparatus of the multi-domain structure, the view angle characteristic has degraded when symmetry in the orientations of the liquid crystal molecules is disordered.
Moreover, in the liquid crystal display apparatus, the uniformity of the display in the entire panel is easily lost due to the voltage drop and the signal delay in the gate bus line and drain bus line. Also, the influence of the backlight light changes the characteristic of the pixel transistor.
Therefore, an object of the present invention is to provide a multi-domain liquid crystal display apparatus of an electrically floating pixel electrode structure can be manufactured with a high production yield and a manufacturing method for the same.
Another object of the present invention is to provide a multi-domain liquid crystal display apparatus of an electrically floating pixel electrode structure which can be formed in a small number of processes and a manufacturing method for the same.
Still another object of the present invention is to provide a multi-domain liquid crystal display apparatus of an electrically floating pixel electrode structure in which a process for forming the pixel electrode is improved, and a manufacturing method for the same.
Yet still another object of the present invention is to provide a multi-domain liquid crystal display apparatus of an electrically floating pixel electrode structure in which display irregularity due to the potential of the bus line or charging of the substrate can be constrained, and symmetry in the orientations of the liquid crystal molecules is secured so that the view angle characteristic is improved.
Also, it is an object of the present invention to provide a multi-domain liquid crystal display apparatus of an electrically floating pixel electrode structure in which the influence of voltage drop in the bus line or backlight light and signal delay can be eased.
In an aspect of the present invention, a liquid crystal display apparatus includes a first substrate, a second substrate and a liquid crystal layer interposed between the first substrate and the second substrate. The first substrate includes on a surface facing the second substrate, a plurality of gate bus lines extending into a row direction, a plurality of drain bus lines extending into a column direction; and a plurality of pixels arranged in matrix. Each of the plurality of pixels includes a portion of one of the plurality of gate bus lines associated with the pixel, a portion of one of the plurality of drain bus lines associated with the pixel, a portion of a capacitance line associated with the pixel, a pixel transistor having a source and a drain which is connected with the associated drain bus line, a control electrode connected with the source and formed in at least a portion of a region of the pixel, and a the pixel electrode which is in an electrically floating state and which is formed to cover the control electrode and a portion of the capacitance line through at least one of a first insulating film and second insulating film.
Here, in the pixel, a first capacitance may be formed from the pixel electrode and the control electrode and a second capacitance may be formed from the pixel electrode and the capacitance line. In this case, it is desirable that the second capacitances are different depending on a distance from a gate signal supply terminal on the associated gate bus line, in a row of the pixels associated with the associated gate bus line. In this case, at least one of the first capacitances and the second capacitances in the row of the pixels are desirably changed such that the change compensates for a voltage drop of a gate signal from the gate signal supply terminal to keep a feed-through voltage of the pixel transistor constant. Also, the second capacitance may be decreased in the row of the pixels depending on the distance from the gate signal supply terminal. Also, an area of the pixel electrode overlapping with the capacitance line portion may be decreased depending on the distance from the gate signal supply terminal in the row of the pixels.
Also, the control electrode may include a conductive layer, and a bordering layer formed in a peripheral portion of the conductive layer.
Also, the pixels adjacent in the column direction are desirably symmetrical with respect to a line extending in the row direction between the pixels. In this case, the associated gate bus line portion is desirably provided in a lower portion of an upper one of the adjacent pixels, and the associated gate bus line portion is desirably provided in an upper portion of a lower one of the adjacent pixels. Also, the capacitance line portion is desirably provided in an upper portion of an upper one of the adjacent pixels, and the capacitance line portion is desirably provided in a lower portion of a lower one of the adjacent pixels.
Also, the associated drain bus line may have two drain lines extending in the row direction between the associated gate bus line portion in the lower portion of the upper pixel and the associated gate bus line portion in the upper portion of the lower pixel. The pixel transistors of the upper and lower pixels are desirably formed to connect with the two drain lines, respectively. In this case, the two drain lines extend toward the drain bus line associated with the pixels adjacent in the row direction.
Also, each of the plurality of pixels may be symmetrical with respect to a centerline thereof extending in the column direction, except for the associated drain bus line portion.
Also, the pixel transistor of each of the plurality of pixels is desirably formed such that the pixel transistor does not stick out of the associated gate bus line portion.
Also, the liquid crystal display apparatus may further include at least one dummy line provided for at least one of a left portion from a leftmost column of the pixels and a right portion from a rightmost column of the pixels in the row direction. In this case, the dummy line is applied with either of a same potential as that of the capacitance line, a same potential as that of adjacent one of the plurality of drain bus lines, a same potential as that of one drain bus line opposite to the associated drain bus line in the plurality of drain bus lines, and an average of potentials of the plurality of drain bus lines.
Also, the liquid crystal display apparatus may further include a conductive film provided on or above a surface of the first substrate on an opposite side to the second substrate.
Also, the pixel transistor may include the associated gate bus line, the first insulating film formed to cover the associated gate bus line, a semiconductor layer formed on the first insulating film, a drain contact layer and a source contact layer formed on the semiconductor layer, and a drain electrode connected to the drain contact layer and a source electrode connected to the source contact layer. In this case, each of the plurality of drain bus lines may be a laminate film composed of a metal film formed of same material as that of the source electrode and the drain electrode of the pixel transistor, and a conductive film formed of same material as that of the control electrode. Also, each of the plurality of drain bus lines may be a laminate film composed of a semiconductor layer formed of same material as that of the semiconductor layer, a metal film formed of same material as that of the source electrode and the drain electrode of the pixel transistor, and a conductive film formed of same material as that of the control electrode.
Also, the pixel transistor may include a drain electrode and a source electrode formed on the facing surface of the first substrate to the second substrate on the first insulating film, a semiconductor layer formed on the insulating film portion, the source electrode and the drain electrode, a third insulating film formed on the semiconductor layer, the gate electrode formed on the third insulation film, and a light shielding layer provided between the first substrate and the first insulating film. Also, the associated gate bus line includes a laminate film may include a semiconductor layer formed of same material as that of the semiconductor layer, an insulating film formed of same material as that of the third insulating film, and a conductive film formed of same material as that of the gate electrode. Also, the source electrode may be a portion of the control electrode.
Also, each of the control electrode and the pixel electrode may be formed of a transparent conductive film, and each of the source electrode and the drain electrode may be formed of at least one of Cr and Mo.
Also, a drain terminal may be formed in each of ends of the plurality of the drain bus lines.
In another aspect of the present invention, a manufacturing method of a liquid crystal display apparatus in which a plurality of pixels are arranged in a matrix in a column direction and a row direction, is achieved by (a) forming a plurality of gate bus lines and a plurality of capacitance lines on a substrate; (b) forming a first insulating film to cover the substrate and the plurality of gate bus lines at least; by (c) forming a plurality of drain bus lines on the first insulating film; by (d) in a region of each of the plurality of pixels, forming a pixel transistor which has a source and a drain on an associated one of the plurality of gate bus lines through the first insulating film, wherein the drain of the pixel transistor is connected with an associated one of the plurality of drain bus lines; by (e) forming a control electrode connected with the source of the pixel transistor in a portion in the pixel region; by (f) forming a second insulating film to cover the first insulating film, the pixel transistor and the plurality of drain bus lines at least; and by (g) forming a pixel electrode in the pixel region to cover the control electrode and a portion of the capacitance line through at least one of the first insulating film and the second insulating film.
Here, the (d) step may be achieved by (h) forming a semiconductor layer and a contact layer on the associated gate bus line through the first insulating film; by (i) patterning the semiconductor layer and the contact layer in an island manner based on a region for the pixel transistor; by (j) forming an electrode layer to cover the contact layer and the semiconductor layer; and by (k) etching the electrode layer to form a source and a drain. In this case, the (e) step of forming the control electrode is carried out subsequent to the (k) step. Also, the (c) step of the drain bus line may be achieved by forming a first conductive layer on the first insulating film at a same time as the (j) step; and by forming a second conductive layer provided on the first conductive layer or covering the first conductive layer at a same time as the (e) step of forming the control electrode.
Also, the (d) step may be achieved by (l) depositing a semiconductor layer, a contact layer and an electrode layer in order on the associated gate bus line through the first insulating film; by (m) patterning the semiconductor layer, the contact layer and the electrode layer in an island manner based on a region for the pixel transistor; by (n) depositing a control electrode film to cover the electrode layer, the contact layer and the semiconductor layer; and by (o) etching the control electrode film, the electrode layer and the contact layer, and forming a source electrode composed of a source contact layer, a lower source electrode on the source contact layer and an upper source electrode on the lower source electrode, and a drain composed of a drain contact layer, a lower drain electrode on the drain contact layer and an upper drain electrode on the lower drain electrode. In this case, the (e) step of forming the control electrode may be carried out at same time as the (n) step and (o) step.
Also, the (c) step of forming the drain bus line may be achieved by patterning a first laminate layer of the semiconductor layer, the contact layer and the electrode layer at a same time as the (m) step; and by forming a first conductive layer provided on or covering the first laminate layer at a same time as the (n) step and the (o) step. In this case, the (m) step may be achieved by patterning the semiconductor layer, the contact layer, the electrode layer and the first insulating film, in each the pixel region. The (n) step may be achieved by depositing the control electrode film to cover the electrode layer and the substrate. Also, the (g) step may be achieved by depositing a pixel electrode film; by forming a resist layer on the pixel electrode film using a halftone mask, wherein the resist layer has a thick portion and a thin portion; by removing the pixel electrode film in a predetermined region using the resist layer; by removing a thin portion of the resist layer by an ashing; and by patterning the pixel electrode film after the removal using the thick portion of the resist layer to form the pixel electrode.
Also, the (d) step may be achieved by (p) depositing a semiconductor layer, a contact layer and an electrode layer in order as a first laminate layer on the gate bus line through the first insulating film; by (q) patterning the electrode layer using a resist pattern to form a source electrode and a drain electrode; by (r) deforming the resist pattern using organic solvent; and by (s) patterning the contact layer and the semiconductor layer in an island manner for a region for the pixel transistor using the deformed resist pattern. In this case, the (e) step of forming the control electrode is desirably carried out subsequent to the (s) step. Also, the (c) step of forming the drain bus line may be achieved by patterning the first laminate layer at same time as the (q) step; and by forming a second conductive layer provided on or covering the first laminate layer at same time as the (e) step.
Also, the (d) step may be achieved by (t) depositing a semiconductor layer, a contact layer and an electrode layer in order as a first laminate layer on the gate bus line through the first insulating film; by (u) forming a resist layer having a thick portion and a thin portion on the electrode layer by changing an integral value of an exposure light quantity; by (v) patterning the electrode layer, the contact layer and the semiconductor layer using the resist pattern in an island manner; by (w) after the thin portion of the resist layer is removed through an ashing process, removing the electrode layer for a channel region of the pixel transistor using the thick portion of the resist layer, to form a source electrode and a drain electrode. In this case, the (e) step of forming the control electrode is desirably carried out the (w) step.
Also, the (c) step of forming the drain bus line may be achieved by patterning the first laminate layer at same time as the (v) step; and by forming a second conductive layer provided on or covering the first laminate layer at same time as the (e) step.
Also, the (g) step of forming the control electrode may be achieved by depositing a pixel electrode film; by forming a resist layer having a thick portion and a thin portion on the pixel electrode film by changing an integral value of an exposure light quantity; by removing the pixel electrode film and the second insulating film or a set of the second insulating film and the first insulating film in a predetermined region in order using the resist layer; by removing the thin portion of the resist layer by an ashing process; and by patterning the pixel electrode film using the thick portion of the resist layer to form the pixel electrode.
Also, the (e) step of forming the control electrode may be achieved by depositing a control electrode film; by depositing a conductive film on the control electrode film; by patterning the conductive film using a resist pattern; and by patterning the control electrode film using the patterned conductive film as a mask.
Also, the (e) step may be achieved by depositing a control electrode film; by patterning the control electrode film; and by forming a conductive film in a peripheral portion of the patterned control electrode film to form the control electrode.
Also, the (e) step may be achieved by depositing a conductive film; by patterning the conductive film to have a loop; by depositing a control electrode film on the patterned conductive film; and by patterning the control electrode film such that an edge portion of the control electrode film is on the patterned conductive film.
Also, the (g) step of forming the pixel electrode may be achieved by depositing a pixel electrode film; by depositing a conductive film on the pixel electrode film; by patterning the conductive film using a resist pattern; and by patterning the pixel electrode film using the patterned conductive film.
Also, the (g) step of forming the pixel electrode may be achieved by depositing a pixel electrode film; by patterning the pixel electrode film; and by forming a conductive film in a peripheral portion of the patterned pixel electrode film to form the pixel electrode.
Also, the (g) step of forming the pixel electrode may be achieved by depositing a conductive film; by patterning the conductive film to have a loop; by depositing a pixel electrode film on the patterned conductive film; and by patterning the control electrode film such that an edge portion of the patterned pixel electrode film is on the patterned conductive film.
Also, a first capacitance may be formed from the pixel electrode and the control electrode and a second capacitance is formed from the pixel electrode and the capacitance line, in each the pixel. The (g) step of forming the pixel electrode may be achieved by forming the pixel electrode in a row of the pixels associated with the associated gate bus line such that the second capacitances are different depending on a distance from a gate signal supply terminal connected to the associated gate bus line.
Also, the (g) step of forming the pixel electrode may be achieved by forming the pixel electrode such that the second capacitances are decreased depending on the distance from the gate signal supply terminal connected to the associated gate bus line in the associated row of the pixels. In this case, the (g) step of forming the pixel electrode may be achieved by forming the pixel electrode such that an overlapping area of the pixel electrode and the capacitance line portion is decreased depending on the distance from the gate signal supply terminal.
Also, the pixel may be formed such that the pixels adjacent in the column direction are symmetrical with respect to a line extending in the row direction between the pixels. In this case, the associated gate bus line portion may be provided in a lower portion of an upper one of the adjacent pixels, and the associated gate bus line portion is provided in an upper portion of a lower one of the adjacent pixels. Also, the capacitance line portion may be provided in an upper portion of an upper one of the adjacent pixels, and the capacitance line portion is provided in a lower portion of a lower one of the adjacent pixels. Also, the step of forming the drain bus line may be achieved by forming two drain lines extending in the row direction between the associated gate bus line portion in the lower portion of the upper pixel and the associated gate bus line portion in the upper portion of the lower pixel. In this case, the pixel transistors of the upper and lower pixels may be formed to be connected with the two drain lines, respectively. Also, the two drain lines may be formed to extend toward the drain bus line associated with the pixels adjacent in the row direction.
Also, each of the plurality of pixels may be formed to be symmetrical with respect to a center line thereof extending in the column direction, except for the associated drain bus line portion.
Also, the pixel transistor of each of the plurality of pixels may be formed such that the pixel transistor does not stick out of the associated gate bus line portion.
Also, the manufacturing method may further comprising the step of: forming at least one dummy line for at least one of a left portion from a leftmost column of the pixels and a right portion from a rightmost column of the pixels in the row direction.
Also, the manufacturing method may further comprise the step of: forming a conductive film provided on or above a surface of the first substrate on an opposite side to the second substrate.
Also, the step of forming the drain bus line further may be achieved by: forming drain terminals in both ends of each of the plurality of drain bus lines.
In still another aspect of the present invention, in a manufacturing method of a liquid crystal display apparatus comprising a plurality of pixels in a matrix in a row direction and a column direction, the manufacturing method may be achieved by (a) forming a plurality of light shielding layers on a substrate; (b) forming a first insulating film to cover the substrate and the plurality of light shielding layers at least; by (c) forming a plurality of drain bus lines; by (d) forming a control electrode in a portion of a region for each of the plurality of pixels; by (e) in the pixel region, forming a pixel transistor above an associated one of the plurality of light shielding layers, wherein the pixel transistor has a source connected to the control electrode, a drain connected with an associated one of the plurality of drain bus lines, and an associated one of a plurality of gate bus lines; by (f) forming a plurality of capacitance lines; by (g) forming a second insulating film to cover the first insulating film, the pixel transistor and the plurality of gate bus lines at least; and by (h) forming a pixel electrode in the pixel region to cover the control electrode and a portion of the capacitance line through at least one of the first insulating film and the second insulating film.
Also, the (e) step may be achieved by (i) forming a source electrode and a drain electrode on the associated light shielding layer through the first insulating film; by (j) after 5-valence element plasma processing is carried out, depositing a and an electrode layer in order; by (k) patterning the electrode layer, the third insulating film and the semiconductor layer to form the plurality of gate bus lines. In this case, the (f) step of forming the plurality of capacitance lines is desirably carried out at same time as the (k) step. Also, the (d) step of forming the control electrode is desirably carried out at same time as the (i) step such that the control electrode and the source electrode are formed unitarily.
Also, the (c) step of forming the plurality of drain bus lines is desirably carried out at same time as the (a) step. Also, the (c) step of forming the plurality of drain bus lines is desirably carried out at same time as the (i) step.
Also, each of the control electrode and the pixel electrode may be formed of a transparent conductive film.
Also, each of the source electrode and the drain electrode may be formed of a refractory metal film.
Also, the (d) step of forming the control electrode may be achieved by depositing a control electrode film; by depositing a conductive film on the control electrode film; by patterning the conductive film using a resist pattern; and by patterning the control electrode film using the patterned conductive film as a mask.
Also, the (d) step may be achieved by depositing a control electrode film; by patterning the control electrode film; and by forming a conductive film in a peripheral portion of the patterned control electrode film to form the control electrode.
Also, the (d) step may be achieved by depositing a conductive film; by patterning the conductive film to have a loop; by depositing a control electrode film on the patterned conductive film; and by patterning the control electrode film such that an edge portion of the control electrode film is on the patterned conductive film.
Also, the (h) step of forming the pixel electrode may be achieved by depositing a pixel electrode film; by depositing a conductive film on the pixel electrode film; by patterning the conductive film using a resist pattern; and by patterning the pixel electrode film using the patterned conductive film.
Also, the (h) step of forming the pixel electrode may be achieved by depositing a pixel electrode film; by patterning the pixel electrode film; and by forming a conductive film in a peripheral portion of the patterned pixel electrode film to form the pixel electrode.
Also, the (h) step of forming the pixel electrode may be achieved by depositing a conductive film; by patterning the conductive film to have a loop; by depositing a pixel electrode film on the patterned conductive film; and by patterning the control electrode film such that an edge portion of the patterned pixel electrode film is on the patterned conductive film.
Also, a first capacitance may be formed from the pixel electrode and the control electrode and a second capacitance is formed from the pixel electrode and the capacitance line, in each the pixel. In this case, the (h) step of forming the pixel electrode may be achieved by forming the pixel electrode in a row of the pixels associated with the associated gate bus line such that the second capacitances are different depending on a distance from a gate signal supply terminal connected to the associated gate bus line. In this case, the (h) step of forming the pixel electrode may be achieved by forming the pixel electrode such that the second capacitances are decreased depending on the distance from the gate signal supply terminal connected to the associated gate bus line in the associated row of the pixels. Also, the (h) step of forming the pixel electrode may be achieved by forming the pixel electrode such that an overlapping area of the pixel electrode and the capacitance line portion is decreased depending on the distance from the gate signal supply terminal.
Also, the pixel may be formed such that the pixels adjacent in the column direction are symmetrical with respect to a line extending in the row direction between the pixels. In this case, the associated gate bus line portion may be provided in a lower portion of an upper one of the adjacent pixels, and the associated gate bus line portion is provided in an upper portion of a lower one of the adjacent pixels. Also, the capacitance line portion may be provided in an upper portion of an upper one of the adjacent pixels, and the capacitance line portion is provided in a lower portion of a lower one of the adjacent pixels. Also, the step of forming the plurality of drain bus lines may be achieved by forming two drain lines extending in the row direction between the associated gate bus line portion in the lower portion of the upper pixel and the associated gate bus line portion in the upper portion of the lower pixel. The pixel transistors of the upper and lower pixels are formed to be connected with the two drain lines, respectively. In this case, the two drain lines may be formed to extend toward the drain bus line associated with the pixels adjacent in the row direction.
Also, each of the plurality of pixels may be formed to be symmetrical with respect to a center line thereof extending in the column direction, except for the associated drain bus line portion.
Also, the pixel transistor of each of the plurality of pixels may be formed such that the pixel transistor does not stick out of the associated gate bus line portion.
Also, the manufacturing method may further comprising the step of: forming at least one dummy line for at least one of a left portion from a leftmost column of the pixels and a right portion from a rightmost column of the pixels in the row direction.
Also, the manufacturing method may further comprise the step of: forming a conductive film provided on or above a surface of the first substrate on an opposite side to the second substrate.
Also, the (c) step of forming the plurality of drain bus lines further may be achieved by: forming drain terminals in both ends of each of the plurality of drain bus lines.